AVR2027: AES Security Module
ثبت نشده
چکیده
Auxialiary Security Header Encrypted NWK payload MIC security information and integrity code (MIC)
منابع مشابه
Low Power Circuit Architecture of AES Crypto Module for Wireless Sensor Network
Recently, much research has been conducted for security for wireless sensor networks and ubiquitous computing. Security issues such as authentication and data integrity are major requirements to construct sensor network systems. Advanced Encryption Standard (AES) is considered as one of candidate algorithms for data encryption in wireless sensor networks. In this paper, we will present the hard...
متن کاملDesign of an Encryption-Decryption Module Oriented for Internet Information Security SOC Design
In order to protect the security of network data, a high speed chip module for encrypting and decrypting of network data packet is designed. The chip module is oriented for internet information security SOC (System on Chip) design. During the design process, AES (Advanced Encryption Standard) and 3DES (Data Encryption Standard) encryption algorithm are adopted to protect the security of network...
متن کاملEnergy Characterization of a Security Module in ARM Processor
This article shows the results obtained during simulations that measured runtime and energy consumption of a security module (SEMO) when it executes in ARM processor. For the simulations, we considered the impacts of four algorithms (i.e. RSA, SHA-1, Random Numbers Generator and AES). We have used the Sim-Panalyzer simulator and obtained an average energy consumption (x2 Joules) and runtime (x2...
متن کاملFPGA Based SCA Resistant AES S-Box Design
A new implementation scheme of AES (Advanced Encryption Standard) is proposed in this paper. The LUT based design of S-box consumes almost 75% of power. Instead of using LUT based S-box, composite field S-box design is used. That can reduce the amount of power consumption. The values of s-box are known to everyone. By masking the each value in the s-box by another masking function increase the ...
متن کاملThe Design of Improved Dynamic AES and Hardware Implementation Using FPGA
ByteSub is a key module in the AES hardware architectures. Most of the ByteSub design is accomplished by look-up table method. To reduce the complexity of AES module and improve the performance and security, we propose a novel dynamic ByteSub generator, which is composed of finite field inverse and multipliers. In our design, look-up table method is no more essential to the ByteSub hardware arc...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2009